library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity counter_fifo_monitor_merger is
  port(
	reset, clk: in std_logic;
	ODL_emp: 	in std_logic_vector (2 downto 0);	    -- monitors SF FIFOs
	i_L_FIFO: 	in std_logic_vector (11 downto 0);    -- input from 12 bit Length FIFO
	i_O_FIFO: 	in std_logic_vector (3 downto 0);     -- input from 3 (now 4) bit Output Port FIFO
	rd_D_FIFO, rd_L_FIFO, rd_O_FIFO: out std_logic;	--read requests for Data, Length, and output FIFOs
	o_xLF: 		out std_logic_vector(11 downto 0); 	    -- 12 bit Length output, connected to each xmit L FIFO
	w_xLF: 		out std_logic_vector (3 downto 0);	    -- 4 bit output to write request, one for each xmit L FIFO 
	w_xDF: 		out std_logic_vector(3 downto 0)	    -- 4 bit output to write request, one for each xmit L FIFO
    );
end counter_fifo_monitor_merger; 
  
architecture main of counter_fifo_monitor_merger is 
-------------------------------------------
	component counterC is
	port( 							
    clk, reset: in std_logic;
    i_read_L: in std_logic;
    o_snd_L:  out std_logic;  --o_hold, 
    i_FIFO_L: in std_logic_vector(11 downto 0);
    i_count: in std_logic_vector(11 downto 0);
    o_count: out std_logic_vector(11 downto 0)
    );
    end component;
-----------------------------------------------
	component SF_FIFO_monitor is
	port( 										-- Signals internal to switch fabric
    clk, reset: in std_logic;
    send_L: in std_logic;  --hold, 
    ODL_emp: in std_logic_vector(2 downto 0);
    i_O_FIFO: in std_logic_vector(3 downto 0);  --input from 3 (now 4) bit Output Port FIFO
    i_L_FIFO: in std_logic_vector(11 downto 0);
    o_L_FIFO: out std_logic_vector(11 downto 0);
    o_read_O, o_read_L, o_read_D: out std_logic;
    xfer_D_req, xfer_L_req: out std_logic_vector(3 downto 0)
	);  
	end component;

--------------------------------------------------------------------
	signal s_read_L, s_send_L: std_logic; 
	signal s_emp: std_logic_vector (2 downto 0);
	signal s_snd_L, s_snd_D: std_logic_vector (3 downto 0);
	signal s_count, si_count, s_L_FIFO: std_logic_vector(11 downto 0); -- s_L_FIFO
begin

SF_ControllerA: SF_FIFO_monitor
	port map (	clk			=>	clk,
		 		reset		=>	reset,  					 
				send_L		=>	s_send_L,
				ODL_emp		=>	ODL_emp,
				i_O_FIFO 	=>	i_O_FIFO, 	
				i_L_FIFO	=>  i_L_FIFO,  	
				o_L_FIFO 	=> 	si_count,
				o_read_O	=>	rd_O_FIFO,	
				o_read_L	=>	s_read_L, 	
				o_read_D	=>	rd_D_FIFO,     
				xfer_D_req	=> 	s_snd_D,	
				xfer_L_req	=>	s_snd_L	);     

SF_Counter: counterC
	port map(	clk			=>	clk, 		
				reset		=>	reset, 	
				i_read_L	=>	s_read_L, 	
				o_snd_L		=>	s_send_L,
				i_FIFO_L	=>	i_L_FIFO, 	
				i_count 	=>  si_count,
				o_count		=>	s_count	);	
			 				
rd_L_FIFO	<=	s_read_L;  	
w_xDF 		<= 	s_snd_D;
o_xLF		<=	s_count + 1;	
w_xLF		<= 	s_snd_L and s_send_L & s_send_L & s_send_l & s_send_L;
end main;
				